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_______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. max3946 1gbps to 11.3gbps, sfp+ laser driver with laser impedance mismatch tolerance 19-5182; rev 1; 5/11 general description the max3946 is a +3.3v, multirate, low-power laser diode driver designed for ethernet and fibre channel transmission systems at data rates up to 11.3gbps. this device is optimized to drive a differential transmit - ter optical subassembly (tosa) with a 25 i flex circuit. the unique design of the output stage enables use of unmatched tosas, greatly reducing headroom limita - tions and lowering power consumption. the device receives differential cml-compatible signals with on-chip line termination. it can deliver laser modula - tion current of up to 80ma, at an edge speed of 22ps (20% to 80%), into a 5 i to 25 i external differential load. the device is designed to have a symmetrical output stage with on-chip back terminations integrated into its outputs. a high-bandwidth, fully differential signal path is implemented to minimize deterministic jitter. an equalization block can be activated to compensate for the sfp+ connector. the integrated bias circuit provides programmable laser bias current up to 80ma. both the laser bias generator and the laser modulator can be dis - abled from a single pin. a 3-wire digital interface reduces the pin count and permits adjustment of input equalization, pulse-width adjustment, tx polarity, tx deemphasis, modulation cur - rent, and bias current without the need for external com - ponents. the max3946 is available in a 4mm x 4mm, 24-pin tqfn package. applications 4x/8x fc sfp+ optical transceivers 10gfc sfp+ optical transceivers 10gbase-lr sfp+ optical transceivers 10gbase-lrm sfp+ optical transceivers oc192-sr xfp/sfp+ sdh/sonet transceivers features s 225mw power dissipation enables < 1w sfp+ modules s up to 100mw power consumption reduction by enabling the use of unmatched fp/dfb tosas s supports sff-8431 sfp+ msa and sff-8472 digital diagnostic s 225mw power dissipation at 3.3v (i mod = 40ma, i bias = 60ma assuming 25 i tosa) s single +3.3v power supply s up to 11.3gbps (nrz) operation s programmable modulation current from 10ma to 100ma (5 i load) s programmable bias current from 5ma to 80ma s programmable input equalization s programmable output deemphasis s 25 i output back termination at tout+ and tout- s dj performance 7ps p-p with mismatched differential load (5 i ) s dj performance 5ps p-p with mismatched differential load (25 i ) s dj performance 5ps p-p with 50 i differential load s programmable pulse width s edge transition times of 22ps s bias current monitor s integrated eye safety features s 3-wire digital interface s -40 c to +95 c operation ordering information note: parts are guaranteed by design and characterization to operate over the -40c to +95c ambient temperature range (t a ) and are tested up to +85c. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. evaluation kit available part temp range pin-package MAX3946ETG+ -40 c to +85 c 24 tqfn-ep*
2 ______________________________________________________________________________________ max3946 1gbps to 11.3gbps, sfp+ laser driver with laser impedance mismatch tolerance stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc , v cct , v ccd ................................................ -0.3v to +4.0v current into tout+ and tout- .................................... +100ma current into tin+ and tin- ............................. -20ma to +20ma voltage range at tin+, tin-, disable, sda, scl, csel, fault, bmax, and bmon ................................ -0.3v to (v cc + 0.3v) voltage range at bias ........................................................ -0.3v to v cc voltage range at tout+ and tout- .... (v cc - 1.3v) to (v cc + 1.3v) current into bias ......................................................................... +130ma continuous power dissipation (t a = +70 n c) tqfn (derate 27.8mw/ n c above +70 n c) .................. 2222mw storage temperature range .......................... -55 n c to +150 n c die attach temperature ................................................. +400 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c electrical characteristics (v cc = +2.85v to +3.63v, t a = -40c to +85c, and figure 1. guaranteed by design and characterization from t a = -40c to +95c. typical values are at v cc = +3.3v, i bias = 60ma, i mod = 40ma, 25 i differential output load, and t a = +25c, unless otherwise noted.) (note 2) absolute maximum ratings package thermal characteristics (note 1) tqfn junction-to-ambient thermal resistance ( q ja ) .......... 36c/w junction-to-case thermal resistance ( q jc ) ................. 3c/w note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . parameter symbol conditions min typ max units power supply power-supply current i cc excludes output current through the exter - nal pullup inductors (note 3) 68 90 ma power-supply voltage v cc 2.85 3.63 v power-supply noise dc to 10mhz 100 mv p-p 10mhz to 20mhz 10 power-on reset v cc for enable high 2.55 2.75 v v cc for enable low 2.3 2.45 v data input specification input data rate 1 10 11.3 gbps differential input voltage v in txeq_en = high, launch amplitude into fr4 transmission line p 5.5in 0.19 0.7 v p-p txeq_en = low 0.15 1.0 differential input resistance r in 75 100 125 i differential input return loss sdd11 part powered on, f p 10ghz 12 db common-mode input return loss scc11 part powered on, 1ghz p f p 10ghz 10 db bias generator maximum bias current i biasmax current into bias pin, disable = low, and tx_en = high 80 ma
_______________________________________________________________________________________ 3 max3946 1gbps to 11.3gbps, sfp+ laser driver with laser impedance mismatch tolerance electrical characteristics (continued) (v cc = +2.85v to +3.63v, t a = -40c to +85c, and figure 1. guaranteed by design and characterization from t a = -40c to +95c. typical values are at v cc = +3.3v, i bias = 60ma, i mod = 40ma, 25 i differential output load, and t a = +25c, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units minimum bias current i biasmin current into bias pin, disable = low, and tx_en = high 5 ma bias-off current i bias-off current into bias pin, disable = high or tx_en = low or set_ibias[8:0] = h0x00; bias pin voltage at v cc 100 f a bias current dac stability 5ma p i bias p 80ma, v bias = v cc - 1.5v (notes 2, 4) 1 3 % instantaneous compliance voltage at bias v bias 0.9 1.5 2.1 v bmon current gain g bmon g bmon = i bmon /i bias , external resistor to ground defines voltage 9 10 11 ma/a compliance voltage at bmon 0 1.8 v bmon current gain stability 5ma p i bias p 80ma (notes 2, 4) 1.2 4 % laser modulator tout+ and tout- instantaneous output compliance voltage v cc - 1.0 v cc + 1.0 v maximum modulation current i modmax current into external 25 i differential termi - nation, output common-mode voltage = v cc 80 ma p-p current into external 50 i differential termi - nation, output common-mode voltage = v cc 60 minimum modulation current i modmin 10 ma p-p differential output resistance 2 x r out 50 i modulation-off maximum current i mod-off current between tout+ and tout- when disable = high or tx_en = low or set_imod[8:0] = h0x00 100 f a modulation current dac stability 10ma p i mod p 80ma (notes 2, 4) 1.5 3 % modulation current edge speed (note 2) t r, t f 20% to 80%, 20ma p i mod p 80ma 22 30 ps 20% to 80%, 10ma p i mod p 80ma, txde_md[1:0] = 3d 22 30 deterministic jitter (notes 2, 5) dj 10ma p i mod p 60ma, 11.3gbps, output differential load = 50 i 5 12 ps p-p 10ma p i mod p 80ma, 11.3gbps, output differential load = 25 i 5 12 10ma p i mod p 80ma, 11.3gbps, output differential load = 5 i 7 10ma p i mod p 60ma, 10.7gbps, output differential load = 50 i (k28.5 pattern) 5 10.5
4 ______________________________________________________________________________________ max3946 1gbps to 11.3gbps, sfp+ laser driver with laser impedance mismatch tolerance electrical characteristics (continued) (v cc = +2.85v to +3.63v, t a = -40c to +85c, and figure 1. guaranteed by design and characterization from t a = -40c to +95c. typical values are at v cc = +3.3v, i bias = 60ma, i mod = 40ma, 25 i differential output load, and t a = +25c, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units random jitter rj 10ma p i mod p 80ma, output differential load = 25 i (note 2) 0.19 0.55 ps rms differential output return loss sdd22 part powered on, f p 5ghz 8 db part powered on, f p 10ghz 6 safety features threshold voltage at bmax v bmax fault always occurs for v bmax r 1.3v, fault never occurs for v bmax < 1.1v (note 2, figure 1) 1.1 1.2 1.3 v threshold voltage at bias v bias fault never occurs for v bias r 0.57v, fault always occurs for v bias < 0.44v 0.44 0.48 0.57 v threshold voltage at bmon v bmon warning always occurs for v bmon r v cc - 0.5v, warning never occurs for v bmon < v cc - 0.7v v cc - 0.7 v cc - 0.6 v cc - 0.5 v sfp timing requirements disable assert time t _off time from rising edge of disable input signal to i bias < i bias-off and i mod < i mod-off 0.05 1 f s disable negate time t _on time from falling edge of disable to i bias and i mod at 90% of steady state 0.5 5 f s fault reset time of power-on time t _init time from power-on or negation of fault using disable 50 200 f s fault reset time t _fault time from fault to fault on, c fault p 20pf, r fault = 4.7k i 0.5 2 f s disable to reset time disable must be held high to reset fault 0.5 f s bias current dac full-scale current i bias-fs set_ibias[8:1] = hxff 80 100 ma lsb size 190 f a integral nonlinearity inl 5ma p i bias p 80ma 0.5 %fs differential nonlinearity dnl 5ma p i bias p 80ma, guaranteed mono - tonic at 8-bit resolution set_ibias[8:1] 0.5 lsb modulation current dac (25 i differential load) full-scale current i mod-fs set_imod[8:1] = hxff 80 105 ma lsb size 200 f a integral nonlinearity inl 10ma p i mod p 80ma q 1 %fs differential nonlinearity dnl 10ma p i mod p 80ma, guaranteed mono - tonic at 9-bit resolution set_imod[8:0] q 0.5 lsb
_______________________________________________________________________________________ 5 max3946 1gbps to 11.3gbps, sfp+ laser driver with laser impedance mismatch tolerance electrical characteristics (continued) (v cc = +2.85v to +3.63v, t a = -40c to +85c, and figure 1. guaranteed by design and characterization from t a = -40c to +95c. typical values are at v cc = +3.3v, i bias = 60ma, i mod = 40ma, 25 i differential output load, and t a = +25c, unless otherwise noted.) (note 2) note 2: guaranteed by design and characterization (t a = -40 n c to +95 n c). note 3: bias is connected to 2.0v. tout+/tout- are connected through pullup inductors to a separate supply that is equal to v cct . note 4: stability is defined as [(i_measured) - (i_reference)]/(i_reference) over the listed current range, temperature, and v cc = v ccref q 5%. v ccref = 3.0v to 3.45v. reference current measured at v ccref , t a = +25 n c. note 5: measured with k28.5 data pattern at 10.7gbps and with a (2 7 - 1 prbs + 72 zeros + 2 7 - 1 prbs (inverted) + 72 ones) pattern at 11.3gbps. parameter symbol conditions min typ max units control i/o specifications disable input current i ih 12 f a i il depends on pullup resistance 500 800 disable input high voltage v ih 1.8 v cc v disable input low voltage v il 0 0.8 v disable input resistance r pull internal pullup resistor 4.7 7.5 10 k i 3-wire digital i/o specifications (sda, scl, csel) input high voltage v ih 2.0 v cc v input low voltage v il 0.8 v input hysteresis v hyst 80 mv input leakage current i il , i ih v in = 0v or v cc , internal pullup or pulldown is 75k i typical 150 f a output high voltage v oh external pullup is (4.7k i to 10k i ) to v cc v cc - 0.5 v output low voltage v ol external pullup is (4.7k i to 10k i ) to v cc 0.4 v 3-wire digital interface timing characteristics (figure 5) scl clock frequency f scl 400 1000 khz scl pulse-width high t ch 0.5 f s scl pulse-width low t cl 0.5 f s sda setup time t ds 100 ns sda hold time t dh 100 ns scl rise to sda propagation time t d 5 ns csel pulse-width low t csw 500 ns csel leading time before the first scl edge t l 500 ns csel trailing time after the last scl edge t t 500 ns sda, scl load c b total bus capacitance on one line with 4.7k i pullup to v cc 20 pf
6 ______________________________________________________________________________________ max3946 1gbps to 11.3gbps, sfp+ laser driver with laser impedance mismatch tolerance figure 1. ac test setup 0.01f scl sda csel v ccd bias v cct 0.01f tin+ tout+ tout- ep tin- 4.7ki 0.01f v cc v cc v eet v cct v eet v ccd disable fault bmax bmon v cct v cct v cc v cc v ccd v cct v cc v cc v cc z 0 = 50i 35i 4.7ki 1ki 1ki 50i 35i 75i 25i 25i 50i 50i 0.01f z 0 = 50i 0.01f 0.01f 0.01f 0.1f sampling oscilloscope 0.1f 2.0v + - 50i 0.01f 0.1f v cct 0.1f max3946
_______________________________________________________________________________________ 7 max3946 1gbps to 11.3gbps, sfp+ laser driver with laser impedance mismatch tolerance typical operating characteristics (v cc = +3.3v, t a = +25c, data pattern = 2 7 - 1 prbs + 72 zeros + 2 7 - 1 prbs (inverted) +72 ones, unless otherwise noted.) 10.3gbps electrical eye diagram max3946 toc02 20ps/div 2 23 - 1 prbs 10.3gbps optical eye diagram max3946 toc01 input differential return loss vs. frequency max3946 toc03 frequency (mhz) sdd11 (db) 10,000 1000 -30 -25 -20 -15 -10 -5 0 -35 100 100,000 input common-mode return loss vs. frequency max3946 toc04 frequency (mhz) scc11 (db) 10,000 -30 -25 -20 -15 -10 -5 0 -35 1000 100,000 input differential to common-mode return loss vs. frequency max3946 toc05 frequency (mhz) scd11 (db) 10,000 1000 -40 -30 -20 -10 0 -50 100 100,000 output differential return loss vs. frequency max3946 toc06 frequency (mhz) sdd22 (db) 10,000 1000 -40 -30 -20 -10 0 -50 100 100,000 output common-mode return loss vs. frequency max3946 toc07 frequency (mhz) scc22 (db) 10,000 1000 -30 -25 -20 -15 -10 -5 0 -35 100 100,000 random jitter vs. modulation current (at load) max3946 toc08 modulation current (ma p-p ) rj (ps rms ) 70 60 40 50 20 30 10 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 0 80 11.3gbps, 25? differential load 1111 0000 pattern
8 ______________________________________________________________________________________ max3946 1gbps to 11.3gbps, sfp+ laser driver with laser impedance mismatch tolerance typical operating characteristics (continued) (v cc = +3.3v, t a = +25c, data pattern = 2 7 - 1 prbs + 72 zeros + 2 7 - 1 prbs (inverted) +72 ones, unless otherwise noted.) supply current vs. temperature (i mod = 40ma p-p , i bias = 60ma) max3946 toc09 temperature (c) supply current (ma) 95 80 65 50 35 20 5 -10 -25 60 70 80 90 100 50 -40 current into v cc , v cct , and v ccd pins total current vs. temperature (i mod at load = 40ma p-p , i bias = 60ma) max3946 toc10 temperature (c) supply current (ma) 95 80 -25 -10 5 35 50 20 65 150 160 170 180 190 200 210 220 140 -40 current into v cc , v cct , and v ccd pins plus modulation and bias current 25? load 5? load eye crossing percent vs. set_pwctrl max3946 toc11 set_pwctrl[3:0] crossing (%) 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 30 35 40 45 50 55 60 65 70 75 25 bias current vs. dac setting max3946 toc12 set_ibias[8:0] bias current (ma) 400 200 20 40 60 80 100 120 0 0 600 modulation current (at load) vs. dac setting max3946 toc13 set_imod[8:0] modulation current (ma p-p ) 400 200 10 20 30 40 50 60 70 80 90 0 0 600 r load = 25? differential r load = 50? differential modulation current deemphasis vs. manual deemphasis setting max3946 toc14 set_txde[5:0] deemphasis (%) 30 20 1 2 3 4 5 6 7 8 9 10 0 10 40 set_imod[8:0] = 230d txde_md[1:0] = 2d bias monitor current vs. temperature max3946 toc15 temperature (c) bmon current (a) 95 80 65 50 35 20 5 -25 -10 100 200 300 400 500 600 700 0 -40 i bias = 60ma i bias = 30ma i bias = 10ma edge speed vs. modulation current max3946 toc16 i mod (ma) edge speed (ps) 80 60 40 20 15 20 25 30 35 40 10 0 100 fall time rise time 25? load, 20% to 80% 10gbps, 11111 00000 pattern edge speed vs. deemphasis setting max3946 toc17 set_txde[5:0] edge speed (ps) 30 20 15 20 25 30 35 40 10 10 40 fall time rise time set_imod[8:0] = 230d 25? load, 20% to 80% 10gbps, 1111 0000 pattern
_______________________________________________________________________________________ 9 max3946 1gbps to 11.3gbps, sfp+ laser driver with laser impedance mismatch tolerance typical operating characteristics (continued) (v cc = +3.3v, t a = +25c, data pattern = 2 7 - 1 prbs + 72 zeros + 2 7 - 1 prbs (inverted) +72 ones, unless otherwise noted.) frequent assertion of disable max3946 toc22 4s/div high high low low v bias fault disable output external fault fault recovery max3946 toc21 4s/div high low low v bias fault disable output external fault removed response to fault max3946 toc20 1s/div high low v bias fault disable output external fault transmitter enable max3946 toc19 1s/div 3.3v high low t_ on = 600ns low v cc fault disable output transmitter disable max3946 toc18 100ns/div 3.3v high low low v cc fault disable output
10 _____________________________________________________________________________________ max3946 1gbps to 11.3gbps, sfp+ laser driver with laser impedance mismatch tolerance pin configuration pin description 23 24 22 21 8 7 9 disable bmax bmon v cct 10 v ccd sda v ccd bias scl v cct 1 2 tin- 4 5 6 17 18 16 14 13 v cc v eet tout+ tout- tout- v cct max3946 fault csel 3 15 tin+ 20 11 tout+ v cc 19 12 v cct v eet thin qfn (4mm 4mm) top view + *ep *exposed pad connected to ground. pin name function 1, 15 v ccd power supply. provides supply voltage to the digital block. 2 disable disable input, cmos. set to logic-low for normal operation. logic-high or open disables both the modulation current and the bias current. internally pulled up by a 7.5k i resistor to v ccd . 3 fault fault output, open drain. logic-high indicates a fault condition. fault remains high even after the fault condition has been removed. a logic-low occurs when the fault condition has been removed and the fault latch has been cleared by toggling the disable pin. fault should be pulled up to v cc by a 4.7k i to 10k i resistor. 4 bmax analog laser bias-current limit. a resistive voltage-divider connected among bmon, bmax, and ground sets the maximum allowed laser bias current limit. the voltage at bmax is internally com - pared to 1.2v bandgap reference voltage. 5 bmon bias current-monitor output. current out of this pin develops a ground-referenced voltage across external resistor(s) that is proportional to the laser bias current. the current sourced by this pin is typically 1/100th the bias pin current. 6, 7, 12, 13 v cct power supply. provides supply voltage to the output block. 8, 9 tout- inverted modulation current output. internally pulled up by a 25 i resistor to v cct . 10, 11 tout+ noninverted modulation current output. internally pulled up by a 25 i resistor to v cct . 14 bias laser bias current connection. this pin requires a 0.1f capacitor to v eet for proper operation. 16 csel chip-select input, cmos. setting csel to logic-high starts a cycle. setting csel to logic-low ends the cycle and resets the control state machine. internally pulled down by a 75k i resistor to v eet . 17 sda serial-data bidirectional input, cmos. open-drain output. this pin has a 75k i internal pullup, but it requires an external 4.7k i to 10k i pullup resistor. (data line-collision protection is implemented.)
______________________________________________________________________________________ 11 max3946 1gbps to 11.3gbps, sfp+ laser driver with laser impedance mismatch tolerance pin description (continued) figure 2. functional diagram eye safety and output control tout+ v cct tout- bias bmon tx_en tx_pol 50i 50i fault tin+ tin- sda scl csel disable bmax laser bias current limiter power-on reset v ccd 7.5ki v ccd v eet v eet v cm 75ki 1 0 pw control 25i 25i eq i mod_dac + i de_dac i bias v cc i bias 100 3-wire interface register control logic set_txeq set_pwctrl 75ki 75ki 9b dac set_imod 6b dac set_txde 9b dac set_ibias max3946 pin name function 18 scl serial-clock input, cmos. this pin has a 75k i internal pulldown. 19, 24 v eet ground 20, 23 v cc power-supply connections. provides supply voltage to the core circuitry. 21 tin+ noninverted data input 22 tin- inverted data input ep exposed pad. ground. must be soldered to circuit board ground for proper thermal and electrical performance (see the exposed-pad package and thermal considerations section).
12 _____________________________________________________________________________________ max3946 1gbps to 11.3gbps, sfp+ laser driver with laser impedance mismatch tolerance detailed description the max3946 sfp+ laser driver is designed to drive 5 i to 50 i tosas from 1gbps to 11.3gbps. the device contains an input buffer with programmable equaliza - tion, pulse-width adjustment, bias current and modula - tion current dacs, output driver with programmable deemphasis, power-on reset circuitry, bias monitor, laser current limiter, and eye-safety circuitry. a 3-wire digital interface is used to control the transmitter functions. the registers that control the devices functionality are txctrl, set_imod, set_ibias, imodmax, ibiasmax, modinc, biasinc, set_txeq, set_pwctrl, and set_txde. input buffer with programmable equalization the input is internally biased and terminated with 50 i to a common-mode voltage. the first amplifier stage fea - tures a programmable equalizer for high-frequency loss - es including sfp connector. equalization is controlled by the set_txeq register and txeq_en bit, txctrl[3] (table 1). the tx_pol bit in the txctrl register con - trols the polarity of tout+ and tout- vs. tin+ and tin-. the set_pwctrl register controls the output eye cross - ing (table 5). a status indicator bit (txed) monitors the presence of an ac input signal. bias current dac the devices bias current is optimized to provide up to 80ma of bias current into a 5 i to 50 i laser load with 200 f a resolution. the bias current is controlled through the 3-wire digital interface using the set_ibias, ibiasmax, and biasinc registers. for laser operation, the laser bias current can be set using the 9-bit set_ibias dac. the upper 8 bits are set by the set_ibias[8:1] register, commonly used during the initialization procedure after por. the lsb (bit 0) of set_ibias is initialized to zero after por and can be updated using the biasinc register. the ibiasmax register should be programmed to a desired maximum bias current value (up to 96ma) to protect the laser. the ibiasmax register limits the maximum set_ibias[8:1] dac code. after initialization the value of the set_ibias dac reg - ister should be updated using the biasinc register to optimize cycle time and enhance laser safety. the biasinc register is an 8-bit register where the first 5 bits contain the increment information in twos comple - ment notation. increment values range from -16 to +15 lsbs. if the updated value of set_ibias[8:1] exceeds ibiasmax[7:0], the ibiaserr warning flag is set and set_ibias[8:0] remains unchanged. modulation current dac the modulation current from the device is optimized to provide up to 80ma of modulation current into a 5 i to 25 i differential laser load (60ma for 50 i laser load) with 300 f a to 200 f a resolution. the modulation current is controlled through the 3-wire digital interface using the set_imod, imodmax, modinc, and set_txde registers. for laser operation, the laser modulation current can be set using the 9-bit set_imod dac. the upper 8 bits are set by the set_imod[8:1] register, commonly used during the initialization procedure after por. the lsb (bit 0) of set_imod is initialized to zero after por and can be updated using the modinc register. the imodmax register should be programmed to a desired maximum modulation current value (up to 96ma) to protect the laser. the imodmax register limits the maximum set_imod[8:1] dac code. table 1. input equalization control register settings txctrl[3] set_txeq[2:1] description txeq_en 0 x x 150mv p-p to 1000mv p-p differential input amplitude (default setting) 1 0 0 optimized for 1in to 4in fr4, 190mv p-p to 450mv p-p differential launch amplitude from source 1 0 1 optimized for 4in to 6in fr4, 190mv p-p to 450mv p-p differential launch amplitude from source 1 1 0 optimized for 1in to 4in fr4, 450mv p-p to 700mv p-p differential launch amplitude from source 1 1 1 optimized for 4in to 6in fr4, 450mv p-p to 700mv p-p differential launch amplitude from source
______________________________________________________________________________________ 13 max3946 1gbps to 11.3gbps, sfp+ laser driver with laser impedance mismatch tolerance after initialization the value of the set_imod dac reg - ister should be updated using the modinc register to optimize cycle time and enhance laser safety. the modinc register is an 8-bit register where the first 5 bits contain the increment information in twos comple - ment notation. increment values range from -16 to +15 lsbs. if the updated value of set_imod[8:1] exceeds imodmax[7:0], the imoderr warning flag is set and set_imod[8:0] remains unchanged. modulation current sent to the laser is actually the com - bination of the current generated by the set_imod reg - ister and current subtracted from this by the set_txde register. output driver the output driver is optimized for a 5 i to 50 i differen - tial load. the output stage also features programmable deemphasis that can be set as a percentage of the mod - ulation current. the deemphasis function is controlled by the txde_md[1] and txde_md[0] bits (txctrl[5:4]) and set_txde[5:0]. power-on reset (por) por ensures that the laser is off until supply voltage has reached a specified threshold (2.75v). after por, bias current and modulation current ramps are controlled to avoid overshoot. in the case of a por, all registers are reset to their default values. bmon and bmax functions current out of the bmon pin is typically 1/100th the value of the current at the bias pin. the total resistance to ground at bmon sets the voltage gain. an internal comparator at the bmax pin latches a fault if the voltage on bmax exceeds the value of 1.2v. the bmax voltage- sense pin is connected by means of a voltage-divider to the bmon pin and ground. the full-scale range of the bmon voltage is 1.2v x (r1/r2 + 1) (figure 3). the ana - log bias-current limit is determined by (1.2v/r2) x 100. eye safety and output control circuitry the safety and output control circuitry includes the dis - able pin (disable) and disable bit (tx_en), along with a fault indicator and fault detectors (figure 4). the device has two types of faults, hard fault and soft fault. a hard fault triggers the fault pin, and the output to the laser is disabled. a soft fault operates as a warning, and the outputs are not disabled. both types of faults are stored in the txstat1 and txstat2 registers. the fault pin is a latched output that can be cleared by toggling the disable pin. toggling the disable pin also clears the txstat1 and txstat2 registers. a sin - gle-point fault can be a short to v cc or ground. table 2 shows the circuit response to various single-point faults. figure 3. bmon and bmax circuitry v cc warning 0.6v bias bmon bmax or if bmax is not used + - fault 100ki r1 r1 r2 1.2v i bias 100 max3946 1ki or if bmon is not used r2 or if bmax and bmon are not used 1ki
14 _____________________________________________________________________________________ max3946 1gbps to 11.3gbps, sfp+ laser driver with laser impedance mismatch tolerance figure 4. eye safety circuitry <0> <1> 0.44v <2> v cc - 2v <3> <4> <6> <7> 1.3v <5> unused v cc - 1.3 v v cc - 0.5v 2.3v fault fault register txstat1 <1> <0> unused set_ibias ibiasmax set_imod imodmax loss-of-signal circuit <2> <3> warning register txstat2 addr = h0x07 v cct tout- tout+ i mod i bias i bias 100 bias v ccd disable 7.5ki bmax bmon reset por fault registers addr = h0x06 v eet v eet v eet
______________________________________________________________________________________ 15 max3946 1gbps to 11.3gbps, sfp+ laser driver with laser impedance mismatch tolerance table 2. circuit response to single-point faults note 1: normaldoes not affect laser power. note 2: supply-shorted current is assumed to be primarily on the circuit board (outside this device), and the main supply is col - lapsed by the short. note 3: normal in functionality, but performance could be affected. warning: shorted to v cc or shorted to ground on some pins can violate the absolute maximum ratings . pin name short to v cc short to ground open 1 v ccd normal disabledhard fault normal (note 3)redundant path 2 disable disabled normal (note 1). can only be dis - abled by other means. disabled 3 fault normal (note 1) normal (note 1) normal (note 1) 4 bmax disabledhard fault normal (note 1) disabledhard fault 5 bmon disabledhard fault normal (note 1) disabledhard fault 6 v cct normal disabledfault (external supply shorted) (note 2) normal (note 3)redundant path 7 v cct normal disabledfault (external supply shorted) (note 2) normal (note 3)redundant path 8 tout- i mod is reduced disabledhard fault i mod is reduced 9 tout- i mod is reduced disabledhard fault i mod is reduced 10 tout+ i mod is reduced disabledhard fault i mod is reduced 11 tout+ i mod is reduced disabledhard fault i mod is reduced 12 v cct normal disabledfault (external supply shorted) (note 2) normal (note 3)redundant path 13 v cct normal disabledfault (external supply shorted) (note 2) normal (note 3)redundant path 14 bias i bias is onno fault disabledhard fault disabledhard fault 15 v ccd normal disabledfault (external supply shorted) (note 2) normal (note 3)redundant path 16 csel normal (note 1) normal (note 1) normal (note 1) 17 sda normal (note 1) normal (note 1) normal (note 1) 18 scl normal (note 1) normal (note 1) normal (note 1) 19 v eet disabledfault (external supply shorted) (note 2) normal normal (note 3)redundant path 20 v cc normal disabledhard fault (external supply shorted) (note 2) normal (note 3)redundant path 21 tin+ soft fault soft fault normal (note 1) 22 tin- soft fault soft fault normal (note 1) 23 v cc normal disabledhard fault (external supply shorted) (note 2) normal (note 3)redundant path 24 v eet disabledfault (external supply shorted) (note 2) normal normal (note 3)redundant path
16 _____________________________________________________________________________________ max3946 1gbps to 11.3gbps, sfp+ laser driver with laser impedance mismatch tolerance 3-wire interface the device implements a proprietary 3-wire digital inter - face. an external controller generates the clock. the 3-wire interface consists of an sda bidirectional data line, an scl clock signal input, and a csel chip-select input (active high). the external master initiates a data transfer by asserting the csel pin. the master starts to generate a clock signal after the csel pin has been set to a logic-high. all data transfers are most significant bit (msb) first. protocol each operation consists of 16-bit transfers (15-bit address/data, 1-bit rwn). the bus master generates 16 clock cycles to scl. all operations transfer 8 bits to the device. the rwn bit determines if the cycle is read or write. see table 3. register addresses the device contains 13 registers available for program - ming. table 4 shows the registers and addresses. write mode (rwn = 0) the master generates 16 total clock cycles at scl. the master outputs a total of 16 bits (msb first) to the sda line at the falling edge of the clock. the master closes the transmission by setting csel to 0. figure 5 shows the interface timing. read mode (rwn = 1) the master generates 16 total clock cycles at scl. the master outputs a total of 8 bits (msb first) to the sda line at the falling edge of the clock. the sda line is released after the rwn bit has been transmitted. the slave out - puts 8 bits of data (msb first) at the rising edge of the clock. the master closes the transmission by setting csel to 0. figure 5 shows the interface timing. mode control normal mode allows read-only instruction for all regis - ters except modinc and biasinc. the modinc and biasinc registers can be updated during normal mode. doing so speeds up the laser control update through the 3-wire interface by a factor of two. the normal mode is the default mode. setup mode allows the master to write unrestricted data into any register except the status (txstat1, txstat2) registers. to enter the setup mode, the modectrl register (address = h0x0e) must be set to h0x12. after the modectrl register has been set to h0x12, the next operation is unrestricted. the setup mode is auto - matically exited after the next operation is finished. this sequence must be repeated if further unrestricted set - tings are necessary. table 3. digital communication word structure table 4. register descriptions and addresses bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 register address rwn data that is written or read address name function h0x05 txctrl transmitter control register h0x06 txstat1 transmitter status register 1 h0x07 txstat2 transmitter status register 2 h0x08 set_ibias bias current setting register h0x09 set_imod modulation current setting register h0x0a imodmax maximum modulation current setting register h0x0b ibiasmax maximum bias current setting register h0x0c modinc modulation current increment setting register h0x0d biasinc bias current increment setting register h0x0e modectrl mode control register h0x0f set_pwctrl pulse-width control register h0x10 set_txde deemphasis control register h0x11 set_txeq equalization control register
______________________________________________________________________________________ 17 max3946 1gbps to 11.3gbps, sfp+ laser driver with laser impedance mismatch tolerance transmitter control register (txctrl) bits 5 and 4: txde_md[1:0]. controls the mode of the transmit output deemphasis circuitry. 00 = deemphasis is fixed at 6.25% of the modulation amplitude 01 = deemphasis is fixed at 3.125% of the modulation amplitude 10 = deemphasis is programmed by the set_txde register setting 11 = deemphasis is at its maximum of approximately 9% bit 3: txeq_en. enables or disables the input equalization circuitry. 0 = disabled 1 = enabled bit 2: softres. resets all registers to their default values (the disable pin must be at a logic 1 during a write to softres for the registers to be set to their default values). 0 = normal 1 = reset bit 1: tx_pol. controls the polarity of the signal path. 0 = inverse 1 = normal bit 0: tx_en. enables or disables the output circuitry. 0 = disabled 1 = enabled figure 5. timing for 3-wire digital interface csel scl sda csel scl sda 1 2 3 4 5 6 7 8 a6 9 1 0 1 1 1 2 1 3 1 4 1 5 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 0 a5 a4 a3 a2 a1 rwn d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 rwn write mode read mode a0 a6 a5 a4 a3 a2 a1 a0 t l t l t ch t cl t ds t dh t ch t cl t ds t d t dh t t t t bit # 7 6 5 4 3 2 1 0 address name x x txde_md[1] txde_md[0] txeq_en softres tx_pol tx_en h0x05 default value x x 0 0 0 0 1 1
18 _____________________________________________________________________________________ max3946 1gbps to 11.3gbps, sfp+ laser driver with laser impedance mismatch tolerance transmitter status register 1 (txstat1) bit 7: fst[7]. when the v cct supply voltage is below 2.3v, the por circuitry reports a fault. once the v cct supply voltage is above 2.75v, the por resets all registers to their default values and the fault is cleared. bit 6: fst[6]. when the voltage at bmon is above v cc - 0.5v, a soft fault is reported. bit 4: fst[4]. when the voltage at bmax goes above 1.3v, a hard fault is reported. bit 3: fst[3]. when the common-mode voltage at v tout q goes below v cc - 1.3v, a soft fault is reported. bit 2: fst[2]. when the voltage at v tout q goes below v cc - 0.8v, a hard fault is reported. bit 1: fst[1]. when the bias voltage goes below 0.44v, a hard fault is reported. bit 0: tx_fault. copy of a fault signal in fst[7:6] and fst[4:1]. a por resets the fst bits to 0. transmitter status register 2 (txstat2) bit 3: imoderr. any attempt to modify set_imod[8:1] above imodmax[7:0] flags a warning at imoderr. (see the programming modulation current section.) bit 2: ibiaserr. any attempt to modify set_ibias[8:1] above ibiasmax[7:0] flags a warning at ibiaserr. (see the programming bias current section.) bit 1: txed. this indicates the absence of an ac signal at the transmit input. bias current setting register (set_ibias) bits 7 to 0: set_ibias[8:1]. the bias current dac is controlled by a total of 9 bits. the set_ibias[8:1] bits are used to set the bias current with even denominations from 0 to 510 bits. the lsb (set_ibias[0]) is controlled by the biasinc register and is used to set the odd denominations in the set_ibias[8:0]. any direct write to set_ibias[8:1] resets the lsb. bit # 7 (sticky) 6 (sticky) 5 (sticky) 4 (sticky) 3 (sticky) 2 (sticky) 1 (sticky) 0 (sticky) address name fst[7] fst[6] x fst[4] fst[3] fst[2] fst[1] tx_fault h0x06 default value x x x x x x x x bit # 7 6 5 4 3 (sticky) 2 (sticky) 1 (sticky) 0 (sticky) address name x x x x imoderr ibiaserr txed x h0x07 default value x x x x x x x x bit # 7 6 5 4 3 2 1 0 address name set_ibias [8] (msb) set_ibias [7] set_ibias [6] set_ibias [5] set_ibias [4] set_ibias [3] set_ibias [2] set_ibias [1] h0x08 default value 0 0 0 0 0 0 0 1
______________________________________________________________________________________ 19 max3946 1gbps to 11.3gbps, sfp+ laser driver with laser impedance mismatch tolerance modulation current setting register (set_imod) bits 7 to 0: set_imod[8:1]. the modulation current dac is controlled by a total of 9 bits. the set_imod[8:1] bits are used to set the modulation current with even denominations from 0 to 510 bits. the lsb (set_imod[0]) is con - trolled by the modinc register and is used to set the odd denominations in the set_imod[8:0]. any direct write to set_imod[8:1] resets the lsb. maximum modulation current setting register (imodmax) bits 7 to 0: imodmax[7:0]. the imodmax register is an 8-bit register that can be used to limit the maximum modula - tion current. imodmax[7:0] is continuously compared to set_imod[8:1]. any attempt to modify set_imod[8:1] above imodmax[7:0] is ignored and flags a warning at imoderr. maximum bias current setting register (ibiasmax) bits 7 to 0: ibiasmax[7:0]. the ibiasmax register is an 8-bit register that can be used to limit the maximum bias current. ibiasmax[7:0] is continuously compared to set_ibias[8:1]. any attempt to modify set_ibias[8:1] above ibiasmax[7:0] is ignored and flags a warning at ibiaserr. modulation current increment setting register (modinc) bit 7: set_imod[0]. this is the lsb of the set_imod[8:0] bits. this bit can only be updated by the use of modinc[4:0]. bits 4 to 0: modinc[4:0]. this string of bits is used to increment or decrement the modulation current. when written to, the set_imod[8:0] bits are updated. modinc[4:0] are a twos complement string. bit # 7 6 5 4 3 2 1 0 address name set_imod [8] (msb) set_imod [7] set_imod [6] set_imod [5] set_imod [4] set_imod [3] set_imod [2] set_imod [1] h0x09 default value 0 0 0 0 0 1 0 0 bit # 7 6 5 4 3 2 1 0 address name imodmax [7] (msb) imodmax [6] imodmax [5] imodmax [4] imodmax [3] imodmax [2] imodmax [1] imodmax [0] (lsb) h0x0a default value 0 0 1 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 address name ibiasmax [7] (msb) ibiasmax [6] ibiasmax [5] ibiasmax [4] ibiasmax [3] ibiasmax [2] ibiasmax [1] ibiasmax [0] (lsb) h0x0b default value 0 0 1 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 address name set_imod [0] (lsb) x x modinc [4] (msb) modinc [3] modinc [2] modinc [1] modinc [0] (lsb) h0x0c default value 0 0 0 0 0 0 0 0
20 _____________________________________________________________________________________ max3946 1gbps to 11.3gbps, sfp+ laser driver with laser impedance mismatch tolerance bias current increment setting register (biasinc) bit 7: set_ibias[0]. this is the lsb of the set_ibias[8:0] bits. this bit can only be updated by the use of biasinc[4:0]. bits 4 to 0: biasinc[4:0]. this string of bits is used to increment or decrement the bias current. when written to, the set_ibias[8:0] bits are updated. biasinc[4:0] are a twos complement string. mode control register (modectrl) bits 7 to 0: modectrl[7:0]. the modectrl register enables the user to switch between normal and setup modes. the setup mode is achieved by setting this register to h0x12. modectrl must be updated before each write opera - tion. exceptions are modinc and biasinc, which can be updated in normal mode. pulse-width control register (set_pwctrl) bits 3 to 0: set_pwctrl[3:0]. this is a 4-bit register used to control the eye crossing by adjusting the pulse width. deemphasis control register (set_txde) bits 5 to 0: set_txde[5:0]. this is a 6-bit register used to control the amount of deemphasis on the transmitter output. when calculating the total modulation current, the amount of deemphasis must be taken into account. the deemphasis is set as a percentage of modulation current. equalization control register (set_txeq) bits 2 to 1: set_txeq[2:1]. these 2 bits are used to control the amount of equalization on the transmitter input. see table 1 for more information. bit # 7 6 5 4 3 2 1 0 address name set_ibias [0] (lsb) x x biasinc [4] (msb) biasinc [3] biasinc [2] biasinc [1] biasinc [0] (lsb) h0x0d default value 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 address name modectrl [7] (msb) modectrl [6] modectrl [5] modectrl [4] modectrl [3] modectrl [2] modectrl [1] modectrl [0] (lsb) h0x0e default value 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 address name x x x x set_pwctrl [3] (msb) set_pwctrl [2] set_pwctrl [1] set_pwctrl [0] (lsb) h0x0f default value x x x x 0 0 0 0 bit # 7 6 5 4 3 2 1 0 address name x x set_txde [5] (msb) set_txde [4] set_txde [3] set_txde [2] set_txde [1] set_txde [0] (lsb) h0x10 default value x x 0 0 0 0 0 1 bit # 7 6 5 4 3 2 1 0 address name x x x x x set_txeq [2] set_txeq [1] x h0x11 default value x x x x x 0 0 x
______________________________________________________________________________________ 21 max3946 1gbps to 11.3gbps, sfp+ laser driver with laser impedance mismatch tolerance design procedure programming bias current 1) ibiasmax[7:0] = maximum_bias_current_value 2) set_ibias i [8:1] = initial_bias_current_value note: the total bias current is calculated using the set_ibias[8:0] dac value. set_ibias[8:1] are the bits that can be manually written. set_ibias[0] can only be updated using the biasinc register. when implementing an apc loop it is recommended to use the biasinc register, which guarantees the fastest bias current update. 3) biasinc i [4:0] = new_increment_value 4) if (set_ibias i [8:1] p ibiasmax[7:0]), then (set_ ibias i [8:0] = set_ibias i-1 [8:0] + biasinc i [4:0]) 5) else (set_ibias i [8:0] = set_ibias i - 1 [8:0]) the total bias current can be calculated as follows: 6) i bias = [set_ibias i [8:0] + 16] x 200 f a programming modulation current 1) imodmax[7:0] = maximum_modulation_current_value 2) set_imod i [8:1] = initial_modulation_current_value x 1.06 note: the total modulation laser current is calculated using the set_imod[8:0] dac value and the set_txde register value. set_imod[8:1] are the bits that can be manually written. set_imod[0] can only be updated using the modinc register. when implementing modulation compensation, it is rec - ommended to use the modinc register, which guaran - tees the fastest modulation current update. 3) modinc i [4:0] = new_increment_value 4) if (set_imod i [8:1] p imodmax[7:0]), then (set_ imod i [8:0] = set_imod i - 1 [8:0] + modinci[4:0]) 5) else (set_imod i [8:0] = set_imod i - 1 [8:0]) the following equations give the modulation current (peak-to-peak) seen at the laser when driven differen - tially. r extd is the differential load impedance of the laser plus any added series resistance. 6a) txde_md[1:0] = 00, then [ ] ( ) [ ] ( ) mod ld 0.3ma set_imod 8 : 0 16 50 i 50 r 0.15ma set_imod 8 : 3 2 ? ? + ? ? ? = ? + ? ? ? + ? ? 6b) txde_md[1:0] = 01, then [ ] ( ) [ ] ( ) mod ld 0.3ma set_imod 8 : 0 16 50 i 50 r 0.15ma set_imod 8 : 4 1 ? ? + ? ? ? = ? + ? ? ? + ? ? 6c) txde_md[1:0] = 10, then set set_txde[5:0] can be set to any value set_imod[8:4] and [ ] ( ) [ ] ( ) mod ld 0.3ma set_imod 8 : 0 16 50 i 50 r 0.15ma set_txde 5:0 1 ? ? + ? ? ? = ? + ? ? ? + ? ? when set_txde[5:0] is increased, the deemphasis current increases and the overall peak-to-peak modu - lation current decreases. this effect saturates when set_txde[5:0] = 0.2 x (set_imod[8:0] + 16) - 1, and further increases to set_txde[5:0] do not increase the deemphasis current. 6d) txde_md[1:0] = 11, then [ ] ( ) mod ld 50 i 0.9 0.3ma set_imod 8 : 0 16 50 r ? ? ? = + ? ? ? + note: when txde_md[1:0] = 10 and the set_txde register is set by the user, the minimum allowed deem - phasis is 3% and the maximum is 10%. these limits are internally set by the max3946. programming transmit output deemphasis 1) txde_md[1:0] = transmit_deemphasis_mode 2) set_txde[5:0] = transmit_deemphasis_value. if txde_md[1:0] = 00, 01, or 11, the value of set_txde is automatically set by the device and there is no need to enter data to set_txde. for transmit_deemphasis_mode: 00 = deemphasis is fixed at 6% of the modulation ampli - tude (the device controls the set_txde value), default setting 01 = deemphasis is fixed at 3% of the modulation ampli - tude (the device controls the set_txde value) 10 = deemphasis is programmed by the set_txde register setting 11 = deemphasis is at its maximum of approximately 9% (the device controls the set_txde value)
22 _____________________________________________________________________________________ max3946 1gbps to 11.3gbps, sfp+ laser driver with laser impedance mismatch tolerance programming pulse-width control the eye crossing at the tx output can be adjusted using the set_pwctrl register. table 5 shows these set - tings. the sign of the number specifies the direction of pulse-width distortion. the code of 1111 corresponds to a balanced state for differential output. the pulse-width distortion is bidirectional around the balanced state (see the typical operating characteristics section). applications information laser safety and iec 825 using the max3946 laser driver alone does not ensure that a transmitter design is compliant with iec 825. the entire transmitter circuit and component selections must be considered. each user must determine the level of fault tolerance required by the application, recognizing that maxim products are neither designed nor authorized for use as components in systems intended for surgical implant into the body, for applications intended to sup - port or sustain life, or for any other application in which the failure of a maxim product could create a situation where personal injury or death could occur. table 5. eye-crossing settings for set_pwctrl table 6. register summary set_pwctrl[3:0] pwd set_pwctrl[3:0] pwd 1000 -7 0111 8 1001 -6 0110 7 1010 -5 0101 6 1011 -4 0100 5 1100 -3 0011 4 1101 -2 0010 3 1110 -1 0001 2 1111 0 0000 1 register function/ address register name normal mode setup mode bit number/ type bit name default value notes transmitter control register address = h0x05 txctrl r rw 5 txde_md[1] 0 msb deemphasis mode r rw 4 txde_md[0] 0 lsb deemphasis mode r rw 3 txeq_en 0 input equalization 0: disabled, 1: enabled r rw 2 softres 0 global digital reset r rw 1 tx_pol 1 tx polarity 0: inverse, 1: normal r rw 0 tx_en 1 tx control 0: disabled, 1: enabled transmitter status register 1 address = h0x06 txstat1 r r 7 (sticky) fst[7] x tx_por tx_vcc low- limit violation r r 6 (sticky) fst[6] x bmon open/shorted to v cc r r 4 (sticky) fst[4] x bmax current exceeded or open/short to ground r r 3 (sticky) fst[3] x v tout+/- common-mode low-limit r r 2 (sticky) fst[2] x v tout+/- low-limit violation r r 1 (sticky) fst[1] x bias open or shorted to ground r r 0 (sticky) tx_fault x copy of fault signal in case por bits 6 to 1 reset to 0
______________________________________________________________________________________ 23 max3946 1gbps to 11.3gbps, sfp+ laser driver with laser impedance mismatch tolerance table 6. register summary (continued) register function/ address register name normal mode setup mode bit number/ type bit name default value notes transmitter status register 2 address = h0x07 txstat2 r r 3 (sticky) imoderr x warning increment result > imodmax r r 2 (sticky) ibiaserr x warning increment result > ibiasmax r r 1 (sticky) txed x tx edge detection bias current setting register address = h0x08 set_ibias r rw 7 set_ibias[8] 0 msb bias dac r rw 6 set_ibias[7] 0 r rw 5 set_ibias[6] 0 r rw 4 set_ibias[5] 0 r rw 3 set_ibias[4] 0 r rw 2 set_ibias[3] 0 r rw 1 set_ibias[2] 0 r rw 0 set_ibias[1] 1 accessible through reg_addr = h0x0d 7 set_ibias[0] 0 lsb bias dac modulation current setting register address = h0x09 set_imod r rw 7 set_imod[8] 0 msb modulation dac r rw 6 set_imod[7] 0 r rw 5 set_imod[6] 0 r rw 4 set_imod[5] 0 r rw 3 set_imod[4] 0 r rw 2 set_imod[3] 1 r rw 1 set_imod[2] 0 r rw 0 set_imod[1] 0 accessible through reg_addr = h0x0c 7 set_imod[0] 0 lsb modulation dac maximum modulation current setting register address = h0x0a imodmax r rw 7 imodmax[7] 0 msb modulation limit r rw 6 imodmax[6] 0 r rw 5 imodmax[5] 1 r rw 4 imodmax[4] 0 r rw 3 imodmax[3] 0 r rw 2 imodmax[2] 0 r rw 1 imodmax[1] 0 r rw 0 imodmax[0] 0 lsb modulation limit maximum bias current setting register address = h0x0b ibiasmax r rw 7 ibiasmax[7] 0 msb bias limit r rw 6 ibiasmax[6] 0 r rw 5 ibiasmax[5] 1 r rw 4 ibiasmax[4] 0 r rw 3 ibiasmax[3] 0 r rw 2 ibiasmax[2] 0 r rw 1 ibiasmax[1] 0 r rw 0 ibiasmax[0] 0 lsb bias limit
24 _____________________________________________________________________________________ max3946 1gbps to 11.3gbps, sfp+ laser driver with laser impedance mismatch tolerance table 6. register summary (continued) register function/ address register name normal mode setup mode bit number/ type bit name default value notes modulation current increment setting register address = h0x0c modinc r r 7 set_imod[0] 0 lsb of set_imod dac register address = h0x09 rw rw 4 modinc[4] 0 msb mod dac twos complement rw rw 3 modinc[3] 0 rw rw 2 modinc[2] 0 rw rw 1 modinc[1] 0 rw rw 0 modinc[0] 0 lsb mod dac twos complement bias current increment setting register address = h0x0d biasinc r r 7 set_ibias[0] 0 lsb of set_ibias dac register address = h0x08 rw rw 4 biasinc[4] 0 msb bias dac twos complement rw rw 3 biasinc[3] 0 rw rw 2 biasinc[2] 0 rw rw 1 biasinc[1] 0 rw rw 0 biasinc[0] 0 lsb bias dac twos complement mode control register address = h0x0e modectrl rw rw 7 modectrl[7] 0 msb mode control rw rw 6 modectrl[6] 0 rw rw 5 modectrl[5] 0 rw rw 4 modectrl[4] 0 rw rw 3 modectrl[3] 0 rw rw 2 modectrl[2] 0 rw rw 1 modectrl[1] 0 rw rw 0 modectrl[0] 0 lsb mode control pulse-width control register address = h0x0f set_ pwctrl r rw 3 set_pwctrl[3] 0 msb tx pulse-width control r rw 2 set_pwctrl[2] 0 r rw 1 set_pwctrl[1] 0 r rw 0 set_pwctrl[0] 0 lsb tx pulse-width con - trol deemphasis control register address = h0x10 set_txde r rw 5 set_txde[5] 0 msb tx deemphasis r rw 4 set_txde[4] 0 r rw 3 set_txde[3] 0 r rw 2 set_txde[2] 0 r rw 1 set_txde[1] 0 r rw 0 set_txde[0] 1 lsb tx deemphasis equalization control register address = h0x11 set_txeq r rw 2 set_txeq[2] 0 tx equalization r rw 1 set_txeq[1] 0
______________________________________________________________________________________ 25 max3946 1gbps to 11.3gbps, sfp+ laser driver with laser impedance mismatch tolerance figure 6. simplified i/o structures layout considerations the data inputs and outputs are the most critical paths for the device and great care should be taken to mini - mize discontinuities on these transmission lines between the connector and the ic. here are some suggestions for maximizing the performance of the ic: ? the data inputs should be wired directly between the module connector and ic without stubs. ? the data transmission lines to the laser should be kept as short as possible and be designed for 50 i differ - ential or 25 i single-ended characteristic impedance. ? an uninterrupted ground plane should be positioned beneath the high-speed i/os. ? ground path vias should be placed close to the ic and the input/output interfaces to allow a return current path to the ic and the laser. ? maintain 100 i differential transmission line imped - ance into the ic. ? use good high-frequency layout techniques and mul - tilayer boards with an uninterrupted ground plane to minimize emi and crosstalk. refer to the schematic and board layers of the max3946 evaluation kit (max3946evkit) for more information. exposed-pad package and thermal considerations the exposed pad on the 24-pin tqfn provides a very low-thermal resistance path for heat removal from the ic. the pad is also electrical ground on the ic and must be soldered to the circuit board ground for proper thermal and electrical performance. refer to application note 862: hfan-08.1: thermal considerations of qfn and other exposed-paddle packages for additional information. 50i 50i v cct v eet tin+ tin- 25i 25i v cct v eet tout+ tout- deemphasis control 7.5ki v ccd v eet disable 75ki v ccd v eet scl, csel v eet fault clamp control loop 75ki v ccd v eet sda
26 _____________________________________________________________________________________ max3946 1gbps to 11.3gbps, sfp+ laser driver with laser impedance mismatch tolerance typical application circuit for 10gbase-lrm host board host filter host filter mode_def2 (sda) mode_def1 (scl) tx_disable rate select tx_fault serdes supply filter supply filter sfp connector v cc (3.3v) v cc (3.3v) 0.1f v ccd r 2 r 1 r pd r mon v eet tin+ tout- tout+ bias bmax bmon scl software 3-wire interface adc i 2 c sda csel 3-wire interface 10g fp-tosa tin- fault disable v cct z diff = 100i z diff = 100i 4.7ki to 10ki v cc v cc v cc fr4 microstrip up to 5.5in 0.1f 0.1f 0.1f fr4 microstrip up to 12in 0.1f 10g linear pin rosa sfp+ optical transceiver max3946 ds1878 sfp controller
______________________________________________________________________________________ 27 max3946 1gbps to 11.3gbps, sfp+ laser driver with laser impedance mismatch tolerance typical application circuit for 10gbase-lr host board host filter host filter mode_def2 (sda) mode_def1 (scl) tx_disable rate select tx_fault serdes supply filter supply filter v cc (3.3v) sfp connector v cc (3.3v) 0.1f v ccd r 2 r 1 r pd r mon v eet v ee v ccr tin+ tout- tout+ bias bmax bmon scl software 3-wire interface adc i 2 c sda csel scl sda csel rpmin rin+ rin- rout- rout+ los caz 3-wire interface 11.3g fp/dfb ldd 11.3g lam 3-wire interface 10g dfb- tosa tin- fault disable v cct z diff = 100i z diff = 100i los 4.7ki to 10ki 4.7ki to 10ki v cc v cc v cc v cc fr4 microstrip up to 5.5in 0.1f 0.1f 0.1f 0.1f fr4 microstrip up to 12in 0.1f 10g pin rosa sfp+ optical transceiver max3946 max3945 ds1878 sfp controller 0.1f
28 _____________________________________________________________________________________ max3946 1gbps to 11.3gbps, sfp+ laser driver with laser impedance mismatch tolerance chip information process: sige bipolar package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 24 tqfn-ep t2444+3 21-0139 90-0021
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 29 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. max3946 1gbps to 11.3gbps, sfp+ laser driver with laser impedance mismatch tolerance revision history revision number revision date description pages changed 0 3/10 initial release 1 5/11 changed the title from 1.0625gbps to 1gbps; changed the edge speed from 20ps to 22ps in the general description and features ; added the package thermal characteristics section; updated graphs 2, 10, 16, and 17 and replaced graphs 6 and 7 in the typical operating characteristics section; updated the bias (requires a 0.1f capacitor to v eet ) and csel (pulled down to v eet rather than gnd) pin descriptions in the pin description table; updated figure 2 scl and csel connec - tions; changed the increment value range from -8 to +7 lsbs to -16 to +15 lsbs in the bias current dac and modulation current dac sections; changed the ground symbols to v eet in figure 4; updated the transmitter control register (txctrl) bit 2 (softres) description; updated figure 6, typical application circuit for 10gbase-lrm , and typical application circuit for 10gbase-lr; added the land pattern no. to the package information table 1, 2, 7, 8, 10, 11, 12, 14, 17, 25C28

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